The invention is directed to the problem of alleviating routing constraints on boards having high pin count devices e.g. devices with a pin count in excess of 1000 pins.
Current ASIC packaging uses a 1 mm spacing (pitch) between pins, which allows maximum package pin counts to be in the order of 2000 pins. Next generation packaging technology is expected to reduce this pitch to 0.8 mm in 2003 and to 0.65 mm by 2005. These pitches will enable packages of 2500 and 3000 pin counts to be implemented, respectively. However, as pin counts increase with decreasing pitch, routing circuit board connections (traces) to the pins becomes more difficult. This is because the pins are arranged in a grid, and with 0.65 mm to 1 mm spacing between pins, there is room enough to route only a single trace between pins. Consequently, multiple layer (or multi-layer) circuit boards are used, wherein each layer provides routing access to a row or two of pins in the grid. For example, a package having a 50×50 grid of pins could require as much as a 35-layer circuit board to route connections to all of its pins. Such high-layer count boards are beyond the range of standard multi-layer board technology, and would therefore be difficult to design, costly to manufacture and risky to use.
So-called “System in Package” (SiP) and multi-chip modules (MCM) are known in the prior art. System in package systems are provided by entities selling services in the design, assembly and test of subsystems. In such designs, one benefits through reduction in routing complexities which results in some degree of simplification. However, simple integration is not sufficient to achieve the kind of gains that are achieved by the present invention. Certain requirements, constraints related to the interconnecting nodes of subsystems must be in place to achieve the substantial difference.
Development of multichip modules tends to be driven by a need to obtain an improvement in device performance. To this end, bare die are integrated on a substrate and packaged in a single package to form a module. Performance improvements using this technology are mainly obtained by having the die in the same package, which leads to shorter connections having more accurately controlled impedances. Although the development of multi-chip modules was not driven by a necessity to reduce routing complexity of circuit boards, the resulting modules have fewer I/O pins than the die that comprise them, thereby alleviating circuit board routing constraints.
Since multi-chip modules incorporate bare die, which often cannot be tested at full operational speed, there is a possibility that some of the die in a module are faulty. Unfortunately, since testing at full operational speed can only be done on a module, if a die in a module is faulty then this will only be discovered when the module is tested. However, since the modules cannot be reworked easily, a faulty die will cause an entire module to be scrapped. Consequently, the production yield of modules is related to the product of the individual yields of its component die. Hence, as the die count in a module increases its production yield decreases. This relationship has made multi-chip modules expensive to produce, and therefore they tend to be used only in cases where they are needed to meet performance requirements.